First TCRTS Workshop on Certifiable Multicore
Avionics Systems (CMAS)



13 April 2015

Starting at 9am


Seattle, WA, USA

Conference Hotel


Multicore computer platforms pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory, I/O bandwidth and interconnections. Much of the real time scheduling for single core chips has centered on the CPU, because it has been the bottleneck resource. The emergence of multicore architectures has moved bottleneck resource away from CPU and towards the now globally shared memory, last level cache, and communication infrastructure.

Temporal coupling among concurrently running applications on different cores makes certification of safety-critical systems particularly challenging. Such problem has been recognized by the Certification Authorities Software Team (CAST), an international group of avionics certification and regulatory representatives from North and South America, Europe, and Asia. In particular, in May of this year CAST released Position Paper 32 on Multi-Core Processors (MCP, see CAST-32) to discuss topics related to safety of avionics software on multicore systems. Among other issues, the position paper identifies MCP Interference Channels, such as shared memory, cache and interconnect features, as possible sources of safety violations. While the position paper does not constitute binding policy on certification, it nevertheless strongly suggests that all such sources of interference must be:

  • identified;
  • analyzed;
  • certifiably mitigated.

Inspired by the CAST-32 position paper, the goal of the workshop is to bring together the Real-Time Systems (RTS) community to address the challenges in the certification of multicore avionics systems. In particular, we will seek contributions from the community on how to analyze and mitigate the effects of interference channels in Commercial-Off-The-Shelf (COTS) multicore processors. Major goals involve:

  • identify the set of timing-related challenges to be addressed;
  • determine which solutions are available for such challenges, and whether the community agrees on a set of such solutions;
  • determine which challenges remain as open problems and
  • The development of an evidence based validation and certification procedure.


We will invite qualified members of the community to present their viewpoints and solutions in the context of CAST-32. Invited speakers will join the workshop’s technical committee. Attendance is open to everyone interested.

The workshop will be full-day and comprise two parts. In the first part, each speaker will be given a slot to present his or her positions and existing results. In the second part, we will host a panel/round table with all members of the technical committee (moderated by the chair). The goal of the round table is to reach an agreement on challenges, solutions and open problems, as discussed in the introduction. Following the workshop, the chairs will coordinate a joint position paper by the workshop’s technical committee to be shared with CAST.


The Workshop will follow the program below:

Lower Level 5 (LL5)
8:30 am

Demystifying the FAA and Multi-Cores

  • speaker5


Lower Level 5 (LL5)
9:15 am
10.00 am
Lower Level 5 (LL5)
10:30 am
Talk 1

Adding Cache and Memory Management to the MC2 (Mixed Criticality onMulticore) Framework

  • speaker5


Lower Level 5 (LL5)
11:00 am
Talk 2

Toward certifiable avionics platforms:
Single Core Equivalent (SCE) techniques - Part 1

  • speaker5


  • speaker5


  • speaker5


Lower Level 5 (LL5)
11:30 am
Talk 3

Toward certifiable avionics platforms:
Single Core Equivalent (SCE) techniques - Part 2

  • speaker5


  • speaker5


12.00 pm
Lower Level 5 (LL5)
1:00 pm
Talk 4

Towards Certifiable Resource Sharing in Safety-Critical Multi-Core Real-Time Systems

  • speaker5


Lower Level 5 (LL5)
1:30 pm
Talk 5

Toward Certifiable Sharing of Hardware Resources in Multicore Processors

  • speaker5

    de Niz

Lower Level 5 (LL5)
2:00 pm
Talk 6

Open Architecture Platforms for Avionics Applications: Challenges in Safety
Critical Systems and possible solutions

  • speaker5


2.30 pm
Lower Level 5 (LL5)
3:00 pm
Talk 7

RT-Xen: Real-Time Virtualization for Multicore Embedded Systems

  • speaker5


Lower Level 5 (LL5)
3:30 pm
Talk 8

Consolidation of Real-Time Systems into a Multi-Core Platform

  • speaker5


  • speaker5


Lower Level 5 (LL5)
4:00 pm
Lower Level 5 (LL5)
5:00 pm

Program Co-Chairs

Workshop Organizers


Full List of Speakers


Full List of Panelists



The technical committee, comprising the chairs and all speakers, will produce a position paper to summarize the views expressed during the workshop. The position paper will be hosted on this webpage.

0 0 0 Days
0 0 Hours
0 0 Minutes
0 0 Seconds