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The RT Multicore Project

On a single-core chip, temporal analysis and certification of safety-critical real-time systems have been tractable because of the fundamental assumption on constant worst-case execution time (WCET) of real-time tasks. Multi-core platforms are becoming increasingly popular and offer high computational power at lower cost. Unfortunately, commercial multi-core platforms are not directly suitable to be employed in safety-critical systems. This is because they are designed to optimize average-case performance at the cost of turning a task’s worst-case execution time (WCET) into a random variable with large variance. In multicore architectures, the sharing of caches, interconnect, main memory, and I/O channels delivers, if uncontrolled, unsatisfactory worst-case guarantees and unpredictable temporal behavior. We aim at restoring the constant WCET assumption at the level of each core on a multi-core chip by looking at this problem from two different perspectives: 1) developing a set of OS-level techniques to manage shared multi-core resources, called Single-Core Equivalence (SCE) and 2) using a Memory-Centric real-time scheduling framework.

The Single-Core-Equivalence (SCE) framework includes a set of software-level techniques to provide deterministic and guaranteed allocation of resources in multi-core platforms. Specifically, DRAM and I/O bandwidth, together with shared cache space are the resources managed by this package. Furthermore, SCE includes advanced interfaces for physical memory management. As part of this project a proof-of-concept package, namely AiRTight, is currently developed which is a Linux implementation of proposed SCE framework.

The Memory-Centric Scheduling research aims at designing a novel scheduling framework for multi-core systems that considers shared memory resources as first-class scheduling units. In all those multi-core systems where the memory hierarchy represents the performance bottleneck, memory accesses should be scheduled to achieve high memory utilization by prioritizing the efficient use of memory space and bandwidth over the management of core utilization.

Sponsors

Our research project has been supported by grants on related research and technology transfer needs. Currently, NSF is the sponsor for the basic research of single core equivalent virtual machines theory and technology. ONR supports complexity reduction and control architecture to integrate related technologies for information dominance in distributed systems, in which SCE technology plays a critical role at the node level. Lockheed Martin Corporation (LMC) and Rockwell Collins provided financial and/or in-kind support for the customization of SCE research for their potential advanced product development. In particular the validation tests from LMC Space Systems laboratory provides valuable feedback. Finally, Canadian Research Council’s support of Professor Rodolfo Pellizzoni for his research on the management of DRAM, which is an integral part of SCE technology package.

Releases

The releases for AiRTtight are available through the following Git repository: https://github.com/airtight. You can also browse the repository in our AiRTight page.

Experimental Results

  • You can access the experimental results for our SCE framework here.
  • You can access the experimental and simulation results for our Memory-Centric Scheduling framewrok here.

Publications

[1] R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo, R. Pellizzoni Real-Time Cache Management Framework for Multi-core Architectures (Best student paper award). Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Philadelphia, USA, April 2013
[2] J.-K. Kim, M.-K. Yoon, R. Bradford, L. Sha, Integrated Modular Avionics (IMA) Partition Scheduling with Conflict-Free I/O for Multicore Avionics Systems. Proceedings of the 38th IEEE Computer Software and Applications Conference (COMPSAC). Vasteras, Sweden, 2014
[3] H. Yun, R. Mancuso, Z.-P. Wu, R. Pellizzoni PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms . Proceedings of the IEEE Intl. Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014
[4] H. Yun Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems . Submitted to the IEEE Real-Time Systems Symposium (RTSS), 2014
[5] S. Li, S. Hu, S. Wang, L. Su, T. Abdelzaher, I. Gupta, R. Pace WOHA: Deadline-Aware Map-Reduce Workflow Scheduling Framework over Hadoop Cluster . Proceedings of the 34th International Conference on Distributed Computing Systems (ICDCS). Madrid, Spain, 2014
[6] S. Li, S. Hu, S. Wang, S. Gu, C. Pan, T. Abdelzaher WattValet: Heterogenous Energy Storage Management in Data Centers for Improved Power Capping . Proceedings of the 11th International Conference on Autonomic Computing (ICAC). Philadelphia, PA, 2014
[7] F. Abdi , J. V. D. Woude, Y. Lu, S. Bak, M. Caccamo, L. Sha, R. Mancuso, S. Mohan On-Chip Control Flow Integrity Check for Real Time Embedded Systems . Proceedings of the 1st IEEE Intl. Conference on Cyber-Physical Systems, Networks and Applications (CPSNA). Taipei, Taiwan, August 2013
[8] R. Mancuso, Or D. Dantsker, M. Caccamo, M. S. Selig A Low-Power Architecture for High Frequency Sensor Acquisition in Many-DOF UAVs . Proceedings of the 5th Intl. Conference on Cyber-Physical Systems (ICCPS). Berlin, Germany, April 2014
[9] O. D. Dantsker, R. Mancuso, M. S. Selig, M. Caccamo High-Frequency Sensor Data Acquisition System (SDAC) for Flight Control And Aerodynamic Data Collection Research on Small to Mid-Sized UAVs . Proceedings of the AIAA Aviation and Aeronautics Forum and Exposition, Applied Aerodynamic Conference, (APA'14). Atlanta, Georgia, June 2014
[10] O. D. Dantsker, R. Mancuso, M. S. Selig, M. Caccamo Robust Sensor Fusion for State Estimation on Agile Electric UAVs . Submitted to the IEEE Real-Time Systems Symposium (RTSS). 2014
[11] R. Mancuso, R. Dudko, M. Caccamo Light-PREM: Automated Software Refactoring for Predictable Execution on COTS Embedded Systems . Proceedings of the IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China, August 2014
[12] R. Mancuso, P. Srivastava, D. Chen, M. Caccamo A Hardware Architecture to Deploy Complex Multiprocessor Scheduling Algorithms . Proceedings of the IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China, August 2014
[13] G. Yao, R. Pellizzoni, S. Bak, H. Yun and M. Caccamo Global Real-Time Memory-Centric Scheduling for Multicore Systems . Submitted to IEEE Transactions on Computers, December 2013
[14] H. Yun, G. Yao, R. Pellizzoni, M. Caccamo and L. Sha Memory Bandwidth Management for Efficient Performance Isolation in Multi-core Platforms . Submitted to IEEE Transactions on Computers, September 2013
[15] G. Yao, H. Yun, Z.-P. Wu, R. Pellizzoni, M. Caccamo, L. Sha Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems . Major Revision Submitted to IEEE Transactions on Computers, August 2013
[16] S. Bak, F. Abdi, Z. Huang, M. Caccamo Using Run-Time Checking to Provide Safety and Progress for Distributed Cyber-Physical Systems . Proceedings of the IEEE conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'13), Taipei, Taiwan, August 2013
[17] H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, L. Sha MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multi-core Platforms. Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Philadelphia, USA, April 2013