Single Core Equivalence @ RTAS14 - Safety-Criticality on Multi-Core made easy

Multi-Core computer platforms pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory and I/O bandwidth. Read our SCE Technical Report

Much of the real time scheduling for single core chips has centered on the CPU, because it has been the bottleneck resource. The emergence of multicore architectures has moved bottleneck resource away from CPU and towards the now globally shared memory banks, memory controllers, last level cache, and I/O channels.

This tutorial presents new technological advancements and solutions to tackle this industry-wide challenge; it introduces the notion of Single Core Equivalent (SCE) software architecture for multicore systems. If managed according to SCE policies, each core can be treated as stand‐alone single-core chip from the point of view of real-time schedulability analysis and certification process. Without a technology like SCE, the change of workload in one core could result in uncontrolled adverse impact on the schedulability of tasks in other cores, triggering the recertification of safety critical applications running in other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the avionic industry. For example, assume that companies A, B, C, D were given IMA partitions in core 1 and their applications were certified. Now, if an application of company E in Core 2 invalidates the schedulability of core 1’s applications, who should do the modification, recertification and pay the bill? Is company E qualified to do the work for companies A, B, C and D? Suppose that Company E pays A, B, C and D to make the changes. What if the modification in Core 1 now invalidates company E’s software schedulability in core 2? Skyrocketing integration costs aside, how can we sort out such circular liability mess?

This tutorial examines the effects of both storage and I/O channel bottlenecks and how to deal with them; it introduces the key theoretical concepts behind SCE and reviews the main implementation aspects faced when trying to implement the SCE architecture framework on modern commercial‐off‐the‐shelf multicore platforms.

Funding: this research is supported by the
National Science Foundation through grant
CNS-1219064 and grant CNS-1302563.

Single-Core Equivalence Technology

Software executing in different cores of a multicore chip can severely interfere with each other due to the share of DRAM, memory bandwidth, last level cache and I/O channels. The single core equivalence (SCE) technology creates real time virtual machines for each core that allows engineers to treat each core as if it were a core in a single core chip. Under SCE, the worst case inter-core interferences are both small and accounted for in the analysis. Figure1 illustrates the difference with or without SCE technology using industry benchmarks.

Critical software can be slowed by up to 6x if uncontrolled

A business perspective

Industries engaged in real time mission critical and/or safety critical applications such as avionics have a large installed base of software developed for single core chips. System integration and certification is one of the most expensive and time consuming tasks in the development of software.

Without SCE technology, software porting, development and integration will incur cost explosion, because many software applications are developed in parallel. When a subcontractor company has validated its software using an assigned core, the subcontractor will work on another task or contract. Without SCE, the software developed later in other cores could cause these validated software to miss their deadlines. This is nightmare in system integration and contract management. This is particularly acute when applications require certifications. In avionics the integrated modular avionics (IMA) standard requires that for any software failures in any IMA partition, failures and recovery cannot take away computing resources allocated to other IMA partitions. If this rule is not enforced, then the failures in one partition can lead to cascaded timing failures across cores. Without SCE, this rule is not enforceable in multicore. SCE technology and management tool allow developers in avionics, automobile, medical equipment, robotics and industrial control systems to port, develop, integrate, analyze, test and certify real time software by reusing the technology and management process developed for single core chips.

Organizers

Lui Sha - University of Illinois at Urbana‐Champaign

Lui Sha graduated with the PhD degree from Carnegie Mellon University in 1985. He is Donald B. Gillies Chair professor of computer science in the University of Illinois at Urbana Champaign. He served on the National Academy of Science’s committee on certifiably dependable software and on the US National Science Foundation’s (NSF) planning committee on cyber physical systems. His work on real‐time computing is supported by the open standards in real time computing and has been cited as an enabling technology to the success of many national high-‐technology projects including GPS upgrade, the Mars Pathfinder, and the International Space Station. He is a fellow of the ACM and a fellow of the IEEE.

Marco Caccamo - University of Illinois at Urbana‐Champaign

Marco Caccamo received the PhD degree in computer engineering from Scuola Superiore Sant’Anna, Italy in 2002. He is an associate professor at the Department of Computer Science, University of Illinois, Urbana‐Champaign. His research interests include real‐time operating systems, real‐time scheduling and resource management, wireless real‐time networks, and quality of service control in next generation digital infrastructures. He has published several papers in major international conferences and journals, and he received the US National Science Foundation (NSF) CAREER Award in 2003. He is a senior member of the IEEE.

Rodolfo Pellizzoni - University of Waterloo

Rodolfo Pellizzoni received the Laurea degree in computer engineering from the University of Pisa in 2004, the Diploma degree from the Scuola Superiore Sant’Anna in 2005, and the PhD degree in computer science from the University of Illinois at Urbana-Champaign in 2010. In September 2010, he joined the Department of Electrical and Computer Engineering at the University of Waterloo as a new assistant professor. His main research interests are in real‐time operating systems, timing analysis, I/O scheduling and novel hardware/software architectures for timing predictability and safety certification. He is a member of the IEEE.

Heechul Yun - University of Kansas

Heechul Yun received the PhD degree in Computer Science from the University of Illinois at Urbana‐Champaign in 2013. He received a BS and a MS degree in Computer Science from KAIST in 1999 and 2001 respectively. Before pursuing PhD, he worked at Samsung Electronics as a senior system software engineer. In August 2013, he joined the Department of Electrical Engineering and Computer Science at the University of Kansas as an assistant professor. His research focuses on operating systems for embedded real-time systems. He is a member of the IEEE.

Renato Mancuso - University of Illinois at Urbana-Champaign

Renato Mancuso is pursuing his PhD in Computer Science at the University of Illinois at Urbana‐Champaign. He received a BS and a MS degree in Computer Engineering from University of Rome "Tor Vergata". He is currently working in the Real-Time and Embedded Systems Lab under the supervision of Prof. Marco Caccamo. His research interests include OS-level techniques for embedded systems to enhance predictability, real-time oriented development of heterogeneous platforms and deployment of unmanned aerial vehicles. He is a member of the IEEE.