• Renato Mancuso

    Embedded Systems Engineer

  • Renato Mancuso

    Embedded Systems Engineer

Publications

Restart-Based Fault-Tolerance: System Design and Schedulability Analysis – Fardin Abdi Taghi Abad, Renato Mancuso, Rohan Tabish and Marco Caccamo

In Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Hsinchu, Taiwan. To Appear.

August 2017

A Scheduling Framework for Handling Integrated Modular Avionic Systems on Multicore Platforms – Alessandra Melani, Renato Mancuso, Marco Caccamo, Giorgio Buttazzo, Johannes Freitag, Sascha Uhrig

In Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Hsinchu, Taiwan. To Appear.

August 2017

WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment Renato Mancuso, Rodolfo Pellizzoni, Neriman Tokcan, Marco Caccamo

In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), Dubrovnik, Croatia. To Appear

June 2017

A Reliable and Predictable OS for Real-Time Embedded Systems – Rohan Tabish, Renato Mancuso, Saud Wasly, Sujit S. Phatak, Rodolfo Pellizzoni, Marco Caccamo

In Proceedings of the 23th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2017). To appear.

April 2017

Optimizing Resource Speed for Two-Stage Real-Time Tasks – Alessandra Melani, Renato Mancuso, Daniel Cullina, Marco Caccamo, Lothar Thiele

Real-Time Sytems Journal

September 2016

Reset-Based Recovery for Real-Time Cyber-Physical Systems with Temporal Safety Constraints – Fardin Abdi, Renato Mancuso, Stanley Bak, Or Dantsker, Marco Caccamo

In Proceedings of the 21st IEEE International Conference on Emerging Technologies Factory Automation and Applications Symposium (ETFA 2016), Berlin, Germany.

September 2016

A Real-Time Scratchpad-centric OS for Multi-core Embedded Systems – Rohan Tabish, Renato Mancuso, Saud Wasly, Ahmed Alhammad, Sujit S. Phatak, Rodolfo Pellizzoni, Marco Caccamo

best presentation award

In Proceedings of the 22th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2016), Vienna, Austria.

April 2016

Speed Optimization for Tasks with Two Resources – Alessandra Melani, Renato Mancuso, Daniel Cullina, Marco Caccamo, Lothar Thiele

In Proceedings of International Conference on Design, Automation & Test in Europe (DATE). Dresden, Germany.

March 2016

Single Core Equivalent Virtual Machines for Hard Real-Time Computing on Multicore Processors – Lui Sha, Marco Caccamo, Rodolfo Pellizzoni, Heechul Yun, Renato Mancuso, Jung Eun Kim, Man-Ki Yoon, Russell Kegley, Dennis Perlman, Greg Arundale, Richard Bradford

IEEE Computer Magazine

February 2016

Using Traffic Phase Shifting to Improve AFDX Link Utilization Renato Mancuso, Andrew V. Louis, Marco Caccamo

In Proceedings of the 15th ACM International Conference on Embedded and Software (EMSOFT). Amsterdam, The Netherlands

October 2015

A Memory Access Detection Methodology for Accurate Workload Characterization – Marco Cesati, Renato Mancuso, Emiliano Betti, Marco Caccamo

In Proceedings of the 21th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Hong Kong, China

August 2015

WCET(m) Estimation in Multi-Core Systems using Single Core Equivalence Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha and Heechul Yun

In Proceedings of the 27th Euromicro Conference on Real-Time Systems (ECRTS 2015), Lund, Sweden

July 2015

A Survey on Cache Management Mechanisms for Predictable Real-Time Embedded Systems – Giovani Gracioli, Ahmed Alhammad, Renato Mancuso, Antonio Augusto Frohlich, Rodolfo Pellizzoni

Accepted for publication on ACM Computing Surveys

September 2015

Exploiting Structured Human Interactions to Enhance Estimation Accuracy in Cyber-physical Systems – Yunlong Gao, Shaohan Hu, Renato Mancuso, Hongwei Wang, Minje Kim, PoLiang Wu , Lu Su , Lui Sha, Tarek Abdelzaher

In Proceedings of the 6th IEEE International Conference on Cyber-Physical Systems (ICCPS 2015), Seattle, WA, USA

April 2015

Light-PREM: Automated Software Refactoring for Predictable Execution on COTS Embedded Systems Renato Mancuso, Roman Dudko, Marco Caccamo

In Proceedings of the 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China

August 2014

A Hardware Architecture to Deploy Complex Multiprocessor Scheduling Algorithms Renato Mancuso, Prakalp Srivastava, Deming Chen, Marco Caccamo

In Proceedings of the 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China

August 2014

A Low-Power Architecture for High Frequency Sensor Acquisition in Many-DOF UAVs Renato Mancuso, Or D. Dantsker, Marco Caccamo, Michael S. Selig

In Proceedings of the 5th IEEE International Conference on Cyber-Physical Systems (ICCPS 2014), Berlin, Germany.

April 2014

PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms – Heechul Yun, Renato Mancuso, Zheng-Pei Wu, Rodolfo Pellizzoni

In Proceedings of the 20th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2014), Berlin, Germany.

April 2014

On-chip Control Flow Integrity Check for Real-Time Embedded Systems – Fardin Abdi Taghi Abad, Joel Van Der Woude, Yi Lu, Stanley Bak, Marco Caccamo, Lui Sha, Renato Mancuso, Sibin Mohan

In Proceedings of the 1st IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA 2013), Taipei, Taiwan.

August 2013

Real-Time Cache Management Framework for Multi-Core Architectures Renato Mancuso, Roman Dudko, Emiliano Betti, Marco Cesati, Marco Caccamo, Rodolfo Pellizzoni

best student paper award

In Proceedings of the 19th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2013), Philadelphia, PA, USA.

April 2013

Single Core Equivalent Virtual Machines for Hard Real-Time Computing on Multicore Processors – Lui Sha, Marco Caccamo, Renato Mancuso, Jung-Eun Kim, Man-Ki Yoon, Rodolfo Pellizzoni, Heechul Yun, Russel Kegley, Dennis Perlman, Greg Arundale, Richard Bradford

Technical Report at UIUC: PDF here

November 2014

Response-Time Analysis for Single Core Equivalence Framework Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha, Heechul Yun

Technical Report at UIUC: PDF here

November 2014

MadT: A Memory Access Detection Tool for Symbolic Memory Profiling – Marco Cesati, Renato Mancuso, Emiliano Betti, Marco Caccamo

Technical Report at UIUC: PDF here

June 2015

Improving Bandwidth Utilization With Deterministic Delivery Guarantees in AFDX through Traffic Phase-Shifting Renato Mancuso, Andrew V. Loius, Marco Caccamo

Technical Report at UIUC: PDF here

September 2015

education

Bachelor Degree in Computer Engineering
University of Rome "Tor Vergata"

Score: 110/110 summa cum laude

Thesis Title: The Coreboot Project

Advisor: Daniel Pierre Bovet

2006-2009

Master Degree in Computer Engineering
University of Rome "Tor Vergata"

Score: 110/110 summa cum laude

Thesis Title: Avoiding Memory Access Conflicts in Real-Time Multi-Core Systems

Advisor: Marco Cesati

2010-2012

Ph.D. Candidate
University of Illinois at Urbana-Champaign

Research Topic: Performance Isolation on Multi-Core Safety-Critical Systems

Advisor: Marco Caccamo

2012-present

Honors / Awards

Award: Best Presentation Award
Paper title: "A Real-Time Scratchpad-centric OS for Multi-core Embedded Systems"

Conference: 22th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2016)

April 2016

Fellowship: CS Excellence Fellowship
Description: The Computer Science Excellence Fellowship is funded thanks to the Graduate College’s Block Grant Program, which provides funds to help departments recruit and retain outstanding graduate students, and thanks to generous donations to the CS @ ILLINOIS general fellowship fund.

Issued by: University of Illinois at Urbana-Champaign - Dept. of Computer Science

Duration: August 2015 - May 2015

Award: Best Student Paper Award
Paper title: "Real-Time Cache Management Framework for Multi-Core Architectures"

Conference: 19th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2013)

April 2013

Patent: Providing Interactive Pharmaceutical Services through Internet
Patent Nr: RM2011A000297

Issuing Industry: CFI PROGETTI S.r.L.

Inventor(s): Renato Mancuso

Submitted: June 2011 - Accepted: May 2014

Summer School: Nano-Tera/Artist International Summer School
Location: Aix-les-Bains, France
Description: The Nano-Tera/Artist International Summer School on Embedded System Design brings together some of the best lecturers from all over the world in a one week programme. Over the years it has proven to be a fantastic opportunity for interaction. We seek a balance between foundational aspects and applications embedded software. Speakers include recognized leading researchers and engineers. The school is open to PhD students, researchers and engineers.

September 2013

Full Merit Scholarship: Collegio Universitario Lamaro-Pozzani
Location: Rome, Italy

Duration: 5 years

Type: Accommodation + Internal Courses

2006-2011

skills and expertise

I have a deep knowledge of operating systems and systems-on-chip.

areas

operating systems (Linux, ErikaOS, Bare-Metal)
architectures
schedulability
embedded systems (ARM, Freescale, Arduino)
mobile development (Android)

Programming Skills

C
C++
Assembly x86/x86_64
Assembly ARM
Assembly PowerPC
Assembly MIPS
Java
PHP/SQL
HTML/JS/CSS

languages skills

  • English

  • Italian

  • Turkish

Project Overview

A brief overview of the projects in which I am currently involved.

Scratchpad-Centric OS

Research Project A novel-paradigm real-time operating system (RTOS) designed to achieve strong inter-core performance isolation and to provide strict timing guarantees on scratchpad-based multi-core COTS platforms. The RTOS is based on Erika Enterprise and targets the automotive domain, with special focus on powertrain systems.

Single-Core Equivalence Framework

Research Project A software and theoretical framework to enforce performance isolation on COTS multi-core systems for safety-critical applications, such as avionics and automotive.

A Robust UAV Platform

Research Project Design and implementation of a platform for UAVs with robustness, fault-tolerance and predictability in mind, together with a focus on low-power operation and low-cost production using COTS components.

AN INTEGRATED HARDWARE SCHEDULER

Research Project Architectural design and implementation of a proof-of-concept hardware scheduler on multi-core hybrid system-on-chips to allow an efficient deployment of complex multiprocessor scheduling algorithms.

Projects

    Single Core Equivalence (SCE)

    Much of the real time scheduling for single core chips has centered on the CPU, because it has been the bottleneck resource. The emergence of multicore architectures has moved bottleneck resource away from CPU and towards the now globally shared memory banks, memory controllers, last level cache, and I/O channels. Single Core Equivalent (SCE) is a OS-level software architecture for multicore systems. If managed according to SCE policies, each core can be treated as stand‐alone single-core chip from the point of view of real-time schedulability analysis and certification process. Without a technology like SCE, the change of workload in one core could result in uncontrolled adverse impact on the schedulability of tasks in other cores, triggering the recertification of safety critical applications running in other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the avionic industry. For example, assume that companies A, B, C, D were given IMA partitions in core 1 and their applications were certified. Now, if an application of company E in Core 2 invalidates the schedulability of core 1’s applications, who should do the modification, recertification and pay the bill? Is company E qualified to do the work for companies A, B, C and D? Suppose that Company E pays A, B, C and D to make the changes. What if the modification in Core 1 now invalidates company E’s software schedulability in core 2? Skyrocketing integration costs aside, how can we sort out such circular liability mess?

    Scratchpad Centric OS

    Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are the shared low level resources, such as the memory hierarchy and the I/O subsystem. With Scratchpad Centric OS, we approach the problem of shared resource arbitration at an OS-level, proposing and implementing a novel design for multi-core platforms revolving around the idea of CPU/memory co-scheduling. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. This project targets scratchpad-based architectures. In this context, we achieve contention-free execution of real-time tasks, while also enforcing a strict separation of application logic and I/O perations in the time domain. To validate the proposed design, we implemented the proposed OS using a commercial-off-the-shelf (COTS) platform. Experiments show that this novel design delivers predictable temporal behavior to hard real-time tasks, and it improves performance up to 2.1x compared to traditional approaches.

    Automatic Code Refactoring with Light-PREM

    As real-time embedded systems become more complex, there is the need to build them using high performance commercial off-the-shelf (COTS) components. However, tasks can exhibit hard to predict worst case execution times (WCET) when executing on commodity hardware, due to contention among shared physical resources. Past work has introduced the PRedictable Execution Model (PREM) to solve this issue, but unfortunately, the time required to manually refactor existing code according to this model is too high. Light-PREM proposes a novel technique that automates the refactoring process needed to convert legacy software applications to PREM-compliant code. The advantage of Light-PREM is twofold. On one side, it makes the adoption of PREM more attractive from an industrial point of view, because it significantly reduces the amount of work that is needed to generate PREM-compliant code. On the other hand, the proposed methodology is general enough to be used with any embedded software design. Experimental results show that Light-PREM significantly improves the predictability of real-time applications without requiring software engineers to gain a deep understanding about software memory usage.

    A Fast, Lightwight and Versatile Data Acquisition System for UAVs

    In this project, we developed a high-frequency sensor data acquisition system (SDAC) for flight control and aerodynamic data collection research on small to mid-sized unmanned aerial vehicles (UAVs). The system is both low weight and low power, operates at 100 Hz and features: a high-frequency, high-resolution six degree-offreedom (6-DOF) inertial measurement unit (IMU) with a global positioning system (GPS) receiver, a 3-axis magnetometer, a pitot probe, seven 10-bit analog-to-digital converters (ADC), sixteen 12-bit analog-to-digital converters, a 14-bit analog-to-digital converter, twenty digital input/outputs (I/O), eight pulse width modulation (PWM) signal inputs, a 40 mile downlink transceiver, an open serial and an open CANbus port, and up to 64 GB of onboard storage. The data acquisition system was completely fabricated from commercial-off-theshelf (COTS) components, which reduced the system cost and implementation time. The SDAC combines the large variety of sensor streams into a unified high-fidelity state data stream that is recorded for later aerodynamics analysis and simultaneously forwarded to a separate processing unit, such as an autopilot.

    Ground Station and UAV Tracking System

    A custom UAV tracking system was implemented on the ground station interface to display sensor and state data and transmit commands to the aircraft instrumentation. The system was designed to provide the human pilot with a quick view of the state of the aircraft. The interface has five sub-displays that show: the physical state of the aircraft, the control inputs, the location of the aircraft; a primary flight display; and a raw input data feed. Along with the displays, the interface has input buttons to start and stop onboard logging and make adjustments to the sub-displays. The system was implemented such that all the aircraft specific data is input into a configuration file, thereby not requiring any modifications to the code to go from aircraft to aircraft. The graphical user interface, which was implemented in a 16:9 ratio to be displayed on today’s high resolution monitors, can be seen in action in the video below.

    Hardware Scheduler + PicOS

    An increasing demand for high-performance systems has been observed in the domain of both general purpose and real-time systems, pushing the industry towards a pervasive transition to multi-core platforms. Unfortunately, well-known and efficient scheduling results for single-core systems do not scale well to the multi-core domain. This justifies the adoption of more computationally intensive algorithms, but the complexity and computational overhead of these algorithms impact their applicability to real OSes. We studied and implemented an architecture to migrate the burden of multi-core scheduling to a dedicated hardware component. We show that it is possible to mitigate the overhead of complex algorithms, while achieving power efficiency and optimizing processors utilization. We develop the idea of 'active monitoring' to continuously track the evolution of scheduling parameters as tasks execute on processors. This allows reducing the gap between implementable scheduling techniques and the ideal fluid scheduling model, under the constraints of realistic hardware.

    Restartable Software/Hardware Architecture

    In traditional computing systems, software problems are often resolved by platform restarts. This approach, however, cannot be naïvely used in cyberphysical systems (CPS). In fact, in this class of systems, ensuring safety strictly depends on the ability to respect hard real-time constraints. Several adaptations of the Simplex architecture have been proposed to guarantee safety in spite of misbehaving software components. However, the problem of performing recovery into a fully operational state has not been extensively addressed. We studied how resets can be used in CPS as an effective strategy to recover from a variety of software faults. Our work extends the Simplex architecture in a number of directions. First, we provide sufficient conditions under which safety is guaranteed in spite of fault-induced resets. Second, we introduce a novel technique to express not only state-dependent safety constraints, as typically done in Simplex, but also time-dependent safety properties. Finally, through a proof-of-concept minimal implementation on a small R/C helicopter and simulation-based system modeling, we show the effectiveness of the proposed recovery strategy under the assumed fault model.

Online Resources

travels

Random shots from places where I have been

Example for loading more items...
/* Custom script */