Rodolfo Pellizzoni
University of Waterloo
rpellizz@uwaterloo.ca
13 April 2015
Starting at 9am
Seattle, WA, USA
Conference Hotel
Multicore computer platforms pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory, I/O bandwidth and interconnections. Much of the real time scheduling for single core chips has centered on the CPU, because it has been the bottleneck resource. The emergence of multicore architectures has moved bottleneck resource away from CPU and towards the now globally shared memory, last level cache, and communication infrastructure.
Temporal coupling among concurrently running applications on different cores makes certification of safety-critical systems particularly challenging. Such problem has been recognized by the Certification Authorities Software Team (CAST), an international group of avionics certification and regulatory representatives from North and South America, Europe, and Asia. In particular, in May of this year CAST released Position Paper 32 on Multi-Core Processors (MCP, see CAST-32) to discuss topics related to safety of avionics software on multicore systems. Among other issues, the position paper identifies MCP Interference Channels, such as shared memory, cache and interconnect features, as possible sources of safety violations. While the position paper does not constitute binding policy on certification, it nevertheless strongly suggests that all such sources of interference must be:
Inspired by the CAST-32 position paper, the goal of the workshop is to bring together the Real-Time Systems (RTS) community to address the challenges in the certification of multicore avionics systems. In particular, we will seek contributions from the community on how to analyze and mitigate the effects of interference channels in Commercial-Off-The-Shelf (COTS) multicore processors. Major goals involve:
We will invite qualified members of the community to present their viewpoints and solutions in the context of CAST-32. Invited speakers will join the workshop’s technical committee. Attendance is open to everyone interested.
The workshop will be full-day and comprise two parts. In the first part, each speaker will be given a slot to present his or her positions and existing results. In the second part, we will host a panel/round table with all members of the technical committee (moderated by the chair). The goal of the round table is to reach an agreement on challenges, solutions and open problems, as discussed in the introduction. Following the workshop, the chairs will coordinate a joint position paper by the workshop’s technical committee to be shared with CAST.
The Workshop will follow the program below:
Adding Cache and Memory Management to the MC2 (Mixed Criticality onMulticore) Framework
James
Anderson
Toward certifiable avionics
platforms:
Single Core Equivalent (SCE) techniques - Part 1
Lui
Sha
Marco
Caccamo
Renato
Mancuso
Toward certifiable avionics
platforms:
Single Core Equivalent (SCE) techniques - Part 2
Heechul
Yun
Jung-Eun
Kim
Towards Certifiable Resource Sharing in Safety-Critical Multi-Core Real-Time Systems
Benny
Akesson
Open Architecture Platforms for
Avionics Applications: Challenges in Safety
Critical
Systems and possible solutions
Bernd
Koppenhoefer
Workshop Organizers
Full List of Speakers
Federal Aviation Administration
University of North Carolina
at Chapel Hill
University of Illinois
at Urbana-Champaign
University of Illinois
at Urbana-Champaign
Czech Technical University
Carnegie Mellon University
Airbus Defence and Space
Washington University
in St. Louis
Carnegie Mellon University
University of Illinois
at Urbana-Champaign
Full List of Panelists
The location of CMAS
Main Conference Venue
Conference Banquet
Grand Hyatt Seattle Hotel
Hyatt at Olive 8 Hotel